The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2024
Filed:
Mar. 17, 2022
SK Hynix Inc., Icheon-si Gyeonggi-do, KR;
Jin Woong Kim, Icheon-si Gyeonggi-do, KR;
Mi Seon Lee, Icheon-si Gyeonggi-do, KR;
SK hynix Inc., Icheon-si Gyeonggi-do, KR;
Abstract
A semiconductor die stack includes a base die and core dies stacked over the base die. Each of the base die and the core dies include a semiconductor substrate, a front side passivation layer formed over a front side of the semiconductor substrate, a back side passivation layer over a back side of the semiconductor substrate, a through-via vertically penetrating the semiconductor substrate and the front side passivation layer, and a bump, a support pattern, and a bonding insulating layer formed over the front side passivation layer. Top surfaces of the bump, the support pattern, and the bonding insulating layer are co-planar. The bump is vertically aligned with the through-via. The support pattern is spaced apart from the through-via and the bump. The support pattern includes a plurality of first bars that extend in parallel with each other in a first direction and a plurality of second bars that extend in parallel with each other in a second direction.