The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Nov. 19, 2021
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Devika Sarkar Grant, Rensselaer, NY (US);

Somnath Ghosh, Clifton Park, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76885 (2013.01); H01L 21/02071 (2013.01); H01L 23/53266 (2013.01); H01L 21/31111 (2013.01); H01L 21/32134 (2013.01); H01L 21/32135 (2013.01);
Abstract

Structures in semiconductor devices, and methods for forming the structures, are described. In one embodiment, a hard mask layer of a deposition stack can be etched to pattern a hard mask. An interconnect layer of the deposition stack can be etched using the hard mask to pattern a plurality of metal lines. The hard mask can be removed. A liner layer of the deposition stack can be etched to remove a portion of the liner layer deposited directly on a dielectric layer of the deposition stack. In response to etching the liner layer, a remaining portion of the liner layer can be deposited between the metal lines and the dielectric layer.


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