The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Feb. 17, 2023
Applicant:

Infineon Technologies Llc, San Jose, CA (US);

Inventors:

Ramesh Chettuvetty, Colorado Springs, CO (US);

Vijay Raghavan, Driftwood, CO (US);

Hans Van Antwerpen, Mountain View, CA (US);

Assignee:

Infineon Technologies LLC, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/063 (2023.01); G06F 5/01 (2006.01); G06F 7/544 (2006.01); G06N 3/04 (2023.01); G11C 11/54 (2006.01); G11C 11/56 (2006.01); H03M 1/38 (2006.01);
U.S. Cl.
CPC ...
G06N 3/063 (2013.01); G06F 5/01 (2013.01); G06F 7/5443 (2013.01); G06N 3/04 (2013.01); G11C 11/54 (2013.01); G11C 11/56 (2013.01); H03M 1/38 (2013.01);
Abstract

A method of operation of a semiconductor device that includes the steps of coupling each of a plurality of digital inputs to a corresponding row of non-volatile memory (NVM) cells that stores an individual weight, initiating a read operation based on a digital value of a first bit of the plurality of digital inputs, accumulating along a first bit-line coupling a first array column weighted bit-line current, in which the weighted bit-line current corresponds to a product of the individual weight stored therein and the digital value of the first bit, and converting and scaling, an accumulated weighted bit-line current of the first column, into a scaled charge of the first bit in relation to a significance of the first bit.


Find Patent Forward Citations

Chettuvetty, Ramesh. (2024). In-memory computing architecture and methods for performing mac operations (U.S. Patent No. 12045714). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12045714

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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