The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 23, 2024
Filed:
Aug. 06, 2021
Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;
Boe Technology Group Co., Ltd., Beijing, CN;
Qianwen Jiang, Beijing, CN;
Hao Zhang, Beijing, CN;
Lili Chen, Beijing, CN;
Peng Han, Beijing, CN;
Huidong He, Beijing, CN;
Juanjuan Shi, Beijing, CN;
BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Beijing, CN;
BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;
Abstract
A layout method of a chip includes: determining a logic diagram corresponding to a chip to be laid out and a device list corresponding to the logic diagram; and determining a layout diagram of the chip to be laid out, according to the logic diagram, the device list, and a pre-trained layout mode. The layout diagram includes at least an arrangement position, in the chip to be laid out, of each device in the device list.