The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

May. 13, 2021
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

John Michael Horley, Cambridge, GB;

Michael John Williams, Cambridge, GB;

Mark Salling Rutland, Cambridge, GB;

Alasdair Grant, Cambridge, GB;

Assignee:

Arm Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 11/34 (2006.01); G06F 11/36 (2006.01);
U.S. Cl.
CPC ...
G06F 11/3466 (2013.01); G06F 9/3867 (2013.01); G06F 11/34 (2013.01); G06F 11/3636 (2013.01); G06F 9/3861 (2013.01); G06F 9/3865 (2013.01); G06F 2201/86 (2013.01); G06F 2201/865 (2013.01);
Abstract

A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.


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