The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Oct. 05, 2021
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Prashant Singh, San Jose, CA (US);

Tezaswi Vatsavai Raja, San Jose, CA (US);

Assignee:

NVIDIA Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/3183 (2006.01); G01R 31/28 (2006.01); G01R 31/317 (2006.01); H03K 3/03 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
G01R 31/318328 (2013.01); G01R 31/2824 (2013.01); G01R 31/31725 (2013.01); H03K 3/0315 (2013.01); H03L 7/0995 (2013.01);
Abstract

Silicon test structures are described that enable separate measurement of n-channel metal-oxide semiconductor (NMOS) and p-channel metal-oxide semiconductor (PMOS) transistor delays. NMOS and PMOS specific non-inverting stages may be used to construct a multi-stage ring oscillator. Each of the non-inverting stages generates either a rising or falling primary transition that is determined by either NMOS or PMOS transistors, respectively. The opposing transition for a particular non-inverting stage is triggered by propagation of the primary transition to a subsequent non-inverting stage (producing a 'reset' pulse). A frequency of the ring oscillator is determined by the primary transition and one transistor type (NMOS or PMOS). Specifically, the frequency is determined by the propagation delay of the primary transition through the entire ring oscillator.


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