The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 23, 2024

Filed:

Apr. 20, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Trevor Hubbard, Dallas, TX (US);

Paul Brohlin, Parker, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/12 (2020.01); G01R 1/02 (2006.01); G01R 1/04 (2006.01); G01R 1/067 (2006.01); G01R 1/073 (2006.01); G01R 1/20 (2006.01); G01R 27/26 (2006.01); G01R 31/26 (2020.01); G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
G01R 31/2623 (2013.01); G01R 1/07342 (2013.01);
Abstract

A probe card with a voltage terminal configured to be coupled to a voltage supply and a current terminal configured to be coupled to a current supply. The voltage terminal and the current terminal are configured to be coupled to an input node of a device under test (DUT) field effect transistor (FET) through probe needles. The probe card has an overlap resistor capacitor (RC) element coupled to the input node. The probe card includes an analog to digital (ADC) voltage capture module configured to be coupled to the input node of the DUT FET and to an output node of the DUT FET through the probe needles. The probe card has a resistive element configured to be coupled to the output node of the DUT FET through the probe needles and to an electrically neutral node and an ADC current capture module coupled in parallel to the resistive element.


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