Memory device with ferroelectric charge trapping layer

Abstract

The present disclosure relates to memory devices, in particular, flash memory devices, storage class memory (SCM) devices or dynamic random access memory (DRAM) devices. The disclosure provides a memory device with a ferroelectric trapping layer. In particular, a memory cell for the memory device comprises a layer stack including: a semiconductor layer; a tunnel layer provided directly on the semiconductor layer; a ferroelectric trapping layer provided directly on the tunnel layer; and a conductive gate layer provided directly on the ferroelectric trapping layer. A blocking layer between the ferroelectric trapping layer and the gate layer may be omitted.