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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12040949 B1

PDFFull Text
Date of Patent:
Jul. 16, 2024

Filed:

Nov. 28, 2022

Connecting processors using twisted torus configurations

Applicant:

Google Llc, Mountain View, CA (US);

Inventor:

Brian Patrick Towles, Chapel Hill, NC (US);

Assignee:

Google LLC, Mountain View, CA (US);

Attorney:

Fish & Richardson P.C.

Primary Examiner:

David R Lazaro

Assistant Examiner:

Berhanu Shitayewoldetadik

Int. Cl.
CPC ...
H04L 15/16 (2006.01); G06F 9/455 (2018.01); G06F 15/16 (2006.01); H04L 9/30 (2006.01); H04L 12/24 (2006.01); H04L 29/06 (2006.01); H04L 29/08 (2006.01); H04L 41/12 (2022.01); H04L 49/10 (2022.01); H04L 49/15 (2022.01); H04L 67/10 (2022.01);
U.S. Cl.
CPC ...
H04L 41/12 (2013.01); H04L 49/10 (2013.01); H04L 49/15 (2013.01); H04L 67/10 (2013.01);
Abstract

Methods, systems, and apparatus, including computer programs encoded on computer-storage media, for connecting processors using twisted torus configurations. In some implementations, a cluster of processing nodes is coupled using a reconfigurable interconnect fabric. The system determines a number of processing nodes to allocate as a network within the cluster and a topology for the network. The system selects an interconnection scheme for the network, where the interconnection scheme is selected from a group that includes at least a torus interconnection scheme and a twisted torus interconnection scheme. The system allocates the determined number of processing nodes of the cluster in the determined topology, sets the reconfigurable interconnect fabric to provide the selected interconnection scheme for the processing nodes in the network, and provides access to the network for performing a computing task.

Find Patent Forward Citations

Towles, Brian. (2024). Connecting processors using twisted torus configurations (U.S. Patent No. 12040949). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12040949

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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