The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Mar. 29, 2022
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Jin Woong Kim, Icheon-si, KR;

Sung Kyu Kim, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 21/76841 (2013.01); H01L 21/76898 (2013.01); H01L 24/11 (2013.01); H01L 24/13 (2013.01); H01L 2224/11011 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/81895 (2013.01); H01L 2224/81896 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes forming a first through via surrounded by a liner in a first semiconductor substrate, first-recessing the semiconductor substrate to expose a first portion of the liner covering an end portion of the first through via, and forming a first diffusion barrier layer covering the first-recessed first semiconductor substrate and exposing a second portion of the liner. The method also includes removing the second portion of the liner and second-recessing the first diffusion barrier layer. The method further includes forming a second diffusion barrier layer that covers the second-recessed first diffusion barrier layer and a top portion of the liner from which the second portion is removed and exposes a top surface of the end portion of the first through via.


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