The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Apr. 17, 2023
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Wan-Soon Im, Cheonan-si, KR;

Chulho Kim, Suwon-si, KR;

Kidan Lee, Suwon-si, KR;

Jeong-Soo Lee, Hwaseong-si, KR;

Jina Lee, Seongnam-si, KR;

Sugwoo Jung, Hwaseong-si, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3208 (2016.01); H10K 59/122 (2023.01); H10K 59/131 (2023.01);
U.S. Cl.
CPC ...
G09G 3/3208 (2013.01); H10K 59/131 (2023.02); G09G 2320/0214 (2013.01); G09G 2320/0233 (2013.01); G09G 2340/0435 (2013.01); H10K 59/122 (2023.02);
Abstract

A display device includes a light emitting element including an anode, a cathode, and a light emitting layer between the anode and the cathode, a first transistor connected between the anode and a first power line, the first transistor may be switched by a voltage of a node, a second transistor connected between the first transistor and a data line, the second transistor may be switched by a write scan signal, a third transistor connected between the node and the anode, the third transistor may be switched by a compensation scan signal, a fourth transistor connected between the node and an initialization line, the fourth transistor may be switched by an initialization scan signal, an insulating layer on the first to the fourth transistors, and a light blocking pattern protruding from the insulating layer, the light blocking pattern being adjacent to the third transistor and the fourth transistor.


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