The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Feb. 09, 2021
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventor:

Min Hwan Moon, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01);
U.S. Cl.
CPC ...
G06F 3/0655 (2013.01); G06F 3/0604 (2013.01); G06F 3/0679 (2013.01);
Abstract

Embodiments of the present disclosure relate to a memory system and an operating method thereof. According to exemplary embodiments of the present disclosure, the memory system may calibrate a history read bias until a termination condition is satisfied based on a number of error bits generated in a first read operation. The memory system may reduce the overhead incurred in handling errors that occur during a read operation by reducing the number of error bits that can occur during read operation due to non-optimization of the history read bias value.


Find Patent Forward Citations

Moon, Min. (2024). Memory system and operating method of the memory system for calibrating a history read bias based on a number of error bits generated in a read operation (U.S. Patent No. 12039190). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/12039190

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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