The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Nov. 29, 2022
Applicant:

Japan Display Inc., Tokyo, JP;

Inventors:

Mitsuhiro Sugawara, Tokyo, JP;

Norio Mamba, Tokyo, JP;

Assignee:

Japan Display Inc., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 19/28 (2006.01); G06F 3/041 (2006.01); G09G 3/20 (2006.01); G06F 3/042 (2006.01); G06F 3/044 (2006.01);
U.S. Cl.
CPC ...
G06F 3/04166 (2019.05); G09G 3/2096 (2013.01); G11C 19/28 (2013.01); G06F 3/0412 (2013.01); G06F 3/04184 (2019.05); G06F 3/042 (2013.01); G06F 3/0443 (2019.05); G09G 3/20 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/061 (2013.01);
Abstract

A display device includes: pixels arranged in a display region; photodiodes provided in two or more of the pixels, respectively; a shift register circuit configured to sequentially output an output signal to the pixels and the photodiodes; a switching circuit configured to switch coupling between the shift register circuit and the pixels, and coupling between the shift register circuit and the photodiodes; and a control circuit configured to control a display period for display by the pixels and a detection period for detection by the photodiodes in a time division manner. The control circuit is configured to sequentially output a gate drive signal to the pixels by an operation of the shift register circuit and the switching circuit in the display period, and sequentially output a sensor control signal to the photodiodes by an operation of the shift register circuit and the switching circuit in the detection period.


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