The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Feb. 11, 2022
Applicant:

Neuroblade Ltd., Tel Aviv, IL;

Inventors:

Elad Sity, Kfar Saba, IL;

Eliad Hillel, Herzliya, IL;

Assignee:

NeuroBlade Ltd., Tel-Aviv, IL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/36 (2006.01); G06F 12/06 (2006.01); G06F 12/0802 (2016.01); G06F 12/14 (2006.01); G06F 13/16 (2006.01); G06F 15/78 (2006.01);
U.S. Cl.
CPC ...
G06F 12/0802 (2013.01); G06F 12/0646 (2013.01); G06F 12/1458 (2013.01); G06F 13/1657 (2013.01); G06F 13/1668 (2013.01); G06F 15/786 (2013.01); G06F 2212/1056 (2013.01); G06F 2212/60 (2013.01); G06F 2212/7202 (2013.01);
Abstract

In some embodiments, an integrated circuit may include a substrate and a memory array disposed on the substrate, where the memory array includes a plurality of discrete memory banks. The integrated circuit may also include a processing array disposed on the substrate, where the processing array includes a plurality of processor subunits, each one of the plurality of processor subunits being associated with one or more discrete memory banks among the plurality of discrete memory banks. The integrated circuit may also include a controller configured to implement at least one security measure with respect to an operation of the integrated circuit and take one or more remedial actions if the at least one security measure is triggered.


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