The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 16, 2024

Filed:

Mar. 18, 2021
Applicant:

Vanguard International Semiconductor Singapore Pte. Ltd., Singapore, SG;

Inventors:

You Qian, Singapore, SG;

Humberto Campanella-Pineda, Singapore, SG;

Rakesh Kumar, Singapore, SG;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
B81C 1/00 (2006.01); B06B 1/06 (2006.01); B81B 3/00 (2006.01); H10N 30/06 (2023.01); H10N 30/074 (2023.01); H10N 30/093 (2023.01); H10N 30/87 (2023.01); H10N 39/00 (2023.01); H10N 30/853 (2023.01); H10N 30/88 (2023.01);
U.S. Cl.
CPC ...
B81C 1/00246 (2013.01); B06B 1/06 (2013.01); B81B 3/0021 (2013.01); H10N 30/06 (2023.02); H10N 30/074 (2023.02); H10N 30/875 (2023.02); H10N 39/00 (2023.02); B81B 2201/0271 (2013.01); B81B 2201/032 (2013.01); B81B 2207/015 (2013.01); B81B 2207/096 (2013.01); B81B 2207/115 (2013.01); B81C 2201/0105 (2013.01); B81C 2203/0735 (2013.01); B81C 2203/0771 (2013.01); H10N 30/093 (2023.02); H10N 30/853 (2023.02); H10N 30/883 (2023.02);
Abstract

A method of forming a monolithic integrated PMUT and CMOS with a coplanar elastic, sealing, and passivation layer in a single step without bonding and the resulting device are provided. Embodiments include providing a CMOS wafer with a metal layer; forming a dielectric over the CMOS; forming a sacrificial structure in a portion of the dielectric; forming a bottom electrode; forming a piezoelectric layer over the CMOS; forming a top electrode over portions of the bottom electrode and piezoelectric layer; forming a via through the top electrode down to the bottom electrode and a second via down to the metal layer through the top electrode; forming a second metal layer over and along sidewalls of the first and second via; removing the sacrificial structure, an open cavity formed; and forming a dielectric layer over a portion of the CMOS, the open cavity sealed and an elastic layer and passivation formed.


Find Patent Forward Citations

Loading…