The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Mar. 22, 2023
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Junya Matsuno, Yokohama Kanagawa, JP;

Kensuke Yamamoto, Yokohama Kanagawa, JP;

Ryo Fukuda, Yokohama Kanagawa, JP;

Masaru Koyanagi, Tokyo, JP;

Kenro Kubota, Fujisawa Kanagawa, JP;

Masato Dome, Yokohama Kanagawa, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/06 (2006.01); G11C 11/419 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 19/018521 (2013.01); G11C 7/1048 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01); H03K 19/018571 (2013.01); G11C 7/065 (2013.01); G11C 7/1087 (2013.01); G11C 11/419 (2013.01);
Abstract

A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.


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