The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Mar. 15, 2021
Applicants:

Kabushiki Kaisha Toshiba, Tokyo, JP;

Toshiba Electronic Devices & Storage Corporation, Tokyo, JP;

Inventors:

Toshiki Seshita, Kanagawa, JP;

Yasuhiko Kuriyama, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F 1/02 (2006.01); H03F 3/195 (2006.01); H03F 3/68 (2006.01); H03F 3/72 (2006.01); H04B 1/04 (2006.01); H04B 1/44 (2006.01);
U.S. Cl.
CPC ...
H03F 3/195 (2013.01); H03F 1/0211 (2013.01); H03F 3/68 (2013.01); H03F 3/72 (2013.01); H04B 1/0458 (2013.01); H04B 1/0483 (2013.01); H04B 1/44 (2013.01); H03F 2200/294 (2013.01); H03F 2200/372 (2013.01); H03F 2200/451 (2013.01); H03F 2200/489 (2013.01); H04B 2001/0416 (2013.01);
Abstract

According to one embodiment, a semiconductor circuit includes: an amplifier including an input terminal; an output circuit including a first node connected to the amplifier, and first and second output terminals, the output circuit performing a first output mode using one of the first and second output terminals or a second output mode using the first and second output terminals; and a bypass circuit between the input terminal and the first node. The output circuit includes a first switch between a second node and the first output terminal, a second switch between a third node and the second output terminal, a third switch between the second and third nodes, a first passive circuit connected to the second node, a second passive circuit connected to the third node, and a third passive circuit between the second and third nodes.


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