The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Aug. 17, 2022
Applicant:

Openlight Photonics, Inc., Goleta, CA (US);

Inventors:

Erik Johan Norberg, Santa Barbara, CA (US);

Anand Ramaswamy, Pasadena, CA (US);

Brian Robert Koch, Brisbane, CA (US);

Assignee:

OpenLight Photonics, Inc., Goleta, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0304 (2006.01); H01L 31/0232 (2014.01); H01L 31/0328 (2006.01); H01L 31/109 (2006.01); H01S 5/02 (2006.01); H01S 5/024 (2006.01); H01S 5/026 (2006.01); H01S 5/10 (2021.01); H01S 5/32 (2006.01);
U.S. Cl.
CPC ...
H01L 31/0304 (2013.01); H01L 31/02327 (2013.01); H01L 31/0328 (2013.01); H01L 31/109 (2013.01); H01S 5/02461 (2013.01); H01S 5/3211 (2013.01); H01S 5/3213 (2013.01); H01S 5/021 (2013.01); H01S 5/026 (2013.01); H01S 5/1032 (2013.01); Y02E 10/544 (2013.01);
Abstract

Embodiments of the invention describe apparatuses, optical systems, and methods related to utilizing optical cladding layers. According to one embodiment, a hybrid optical device includes a silicon semiconductor layer and a III-V semiconductor layer having an overlapping region, wherein a majority of a field of an optical mode in the overlapping region is to be contained in the III-V semiconductor layer. A cladding region between the silicon semiconductor layer and the III-V semiconductor layer has a spatial property to substantially confine the optical mode to the III-V semiconductor layer and enable heat dissipation through the silicon semiconductor layer.


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