The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Aug. 22, 2023
Applicants:

Samsung Display Co., Ltd., Yongin-si, KR;

Konkuk University Industrial Cooperation Corp, Seoul, KR;

Inventors:

Kyung Ho Kim, Yongin-si, KR;

Yi Kyoung You, Yongin-si, KR;

Kee Chan Park, Yongin-si, KR;

Sang Yong No, Yongin-si, KR;

Gi Chang Lee, Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01); G09G 3/3233 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G09G 3/3233 (2013.01); G09G 2310/08 (2013.01); G09G 2330/028 (2013.01);
Abstract

A scan signal driver includes: a plurality of stages configured to be driven by dividing a first frame period into a display period and a sensing period, and to sequentially output scan signals at the display period, wherein each of the plurality of stages comprises: an output control circuit; and a memory control circuit, wherein the scan driver is configured to: irregularly set a specific stage of the plurality of stages at a display period every frame; control the specific stage to: store a voltage by using the memory control circuit; and output a sensing signal by using the stored voltage at a sensing period, and the memory control circuit includes: a second memory transistor configured to electrically connect an M node with an I node; and a third memory transistor configured to electrically connect the output control circuit with the I node.


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