The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Jun. 08, 2021
Applicants:

Chengdu Boe Optoelectronics Technology Co., Ltd., Sichuan, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Lei Feng, Beijing, CN;

Shuiming Lv, Beijing, CN;

Weibo Hu, Beijing, CN;

Guoqiang Wu, Beijing, CN;

Chungkee Cheng, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/20 (2006.01); G09G 3/3233 (2016.01);
U.S. Cl.
CPC ...
G09G 3/3233 (2013.01); G09G 3/2096 (2013.01); G09G 2300/0819 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0205 (2013.01); G09G 2310/0286 (2013.01); G09G 2310/08 (2013.01); G09G 2320/0209 (2013.01);
Abstract

A display panel and a drive method therefor, where when a gate electrode drive circuit () scans pixels line-by-line, a drive chip () controls a clock signal end to input a clock control signal (CK) into the gate electrode drive circuit (), which causes a gate electrode scan signal (G(n)) to be output by the gate electrode drive circuit (), and a data signal (Vd) output by a data signal end is controlled to be written to a corresponding row of pixel circuits (). Where an active level period of the clock control signal (CK) falls within an active level period of the data signal (Vd), and a start time for the active level period of the data signal (Vd) is at least 1-2 μs earlier than a start time for the active level period of the clock control signal (CK).


Find Patent Forward Citations

Loading…