The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Mar. 16, 2022
Applicant:

Maxar Space Llc, Palo Alto, CA (US);

Inventors:

Manuel Gonzalez-Rivero, Alexandria, VA (US);

David R. Herdzik, Ypsilanti, MI (US);

Jonathan C. Harris, Ellicott City, MD (US);

Assignee:

Maxar Space LLC, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06V 10/82 (2022.01); G06N 3/048 (2023.01); G06V 10/774 (2022.01); G06N 3/08 (2023.01); G06T 3/4046 (2024.01); G06T 7/10 (2017.01); G06V 10/75 (2022.01); G06V 30/18 (2022.01);
U.S. Cl.
CPC ...
G06V 10/82 (2022.01); G06N 3/048 (2023.01); G06V 10/7747 (2022.01); G06N 3/08 (2013.01); G06T 3/4046 (2013.01); G06T 7/10 (2017.01); G06V 10/751 (2022.01); G06V 30/18086 (2022.01);
Abstract

Methods and structures are presented for implementing an automatic target recognition system as a convolutional neural network (CNN) in a satellite or other environment with constrained resources, such as limited memory capacity and limited processing capability. For example, this allows for the automatic target recognition to be implemented on a field programmable gate array (FPGA). Image data is split into subsets of contiguous pixels, with the subsets processed in parallel in a CNN of a corresponding processing node using quantized weight values that are determined in a training process that accounts for the constraints of the automatic target recognition system. The results of the automatic target recognition process is based on the combined output of the processing nodes.


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