The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Dec. 11, 2020
Applicant:

Rigetti & Co, Llc, Berkeley, CA (US);

Inventors:

Michael Justin Gerchick Scheer, Oakland, CA (US);

Maxwell Benjamin Block, Oakland, CA (US);

Benjamin Jacob Bloom, Oakland, CA (US);

Matthew J. Reagor, Corte Madera, CA (US);

Alexander Papageorge, San Francisco, CA (US);

Kamal Yadav, Fremont, CA (US);

Nasser Alidoust, Berkeley, CA (US);

Colm Andrew Ryan, Albany, CA (US);

Shane Arthur Caldwell, Oakland, CA (US);

Yuvraj Mohan, Fremont, CA (US);

Anthony Polloreno, Carlsbad, CA (US);

John Morrison Macaulay, Emeryville, CA (US);

Blake Robert Johnson, El Cerrito, CA (US);

Assignee:

Rigetti & Co, LLC, Berkeley, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/78 (2006.01); G06F 30/373 (2020.01); G06F 30/392 (2020.01); G06F 30/3947 (2020.01); G06N 10/40 (2022.01);
U.S. Cl.
CPC ...
G06N 10/40 (2022.01); G06F 15/7896 (2013.01); G06F 30/373 (2020.01); G06F 30/392 (2020.01); G06F 30/3947 (2020.01);
Abstract

In a general aspect, a quantum processor has a modular architecture. In some aspects, a modular quantum processor includes first and second quantum processor chips and a cap structure. The first quantum processor chip is supported on a substrate layer and includes a first plurality of qubit devices. The second quantum processor chip is supported on the substrate layer and includes a second plurality of qubit devices. The cap structure is supported on the first and second quantum processor chips and includes a coupler device that provides coupling between at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices. In some instances, the coupler device is an active coupler device that is configured to selectively couple at least one of the first plurality of qubit devices with at least one of the second plurality of qubit devices.


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