The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Jul. 11, 2022
Applicant:

Xilinx, Inc., San Jose, CA (US);

Inventors:

Shantanu Mishra, Hyderabad, IN;

Hemant Kashyap, Hyderabad, IN;

Uday Kyatham, Hyderabad, IN;

Mahesh Attarde, Hyderabad, IN;

Amit Kasat Kasat, Hyderabad, IN;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 8/41 (2018.01);
U.S. Cl.
CPC ...
G06F 8/434 (2013.01); G06F 8/44 (2013.01);
Abstract

Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that specifies an assembly language version of the kernel as instrumented.


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