The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 09, 2024

Filed:

Mar. 05, 2021
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Vishnu Ravinuthula, Dallas, TX (US);

Takao Oshida, Plano, TX (US);

Geoffrey Grimmer, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H02J 7/00 (2006.01); G01R 31/36 (2020.01); G01R 31/396 (2019.01); H03M 1/44 (2006.01);
U.S. Cl.
CPC ...
G01R 31/396 (2019.01); G01R 31/3648 (2013.01); H02J 7/0071 (2020.01); H03M 1/44 (2013.01);
Abstract

An apparatus comprises a plurality of analog front ends (AFEs) adapted to be coupled to a plurality of battery cells and configured to decrease voltages received from the plurality of battery cells to produce a plurality of AFE voltages. The apparatus further comprises at least one analog-to-digital converter (ADC) coupled to the plurality of AFEs and configured to convert the plurality of AFE voltages to a plurality of corresponding digital signals. The apparatus also comprises a plurality of digital channel registers coupled to the at least one ADC and configured to store the plurality of digital signals, and a processor coupled to the at least one ADC and configured to adjust, in a round-robin calculation scheme, the plurality of digital signals based on a plurality of common mode voltage values and a plurality of common mode to differential gain values associated with the plurality of AFEs.


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