The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 02, 2024
Filed:
Feb. 08, 2023
Integrated Silicon Solution, (Cayman) Inc., Grand Cayman, KY;
Thomas Boone, Fremont, CA (US);
Pradeep Adam Manandhar, Fremont, CA (US);
Girish Anthony Jagtini, Fremont, CA (US);
Yuan-Tung D. Chin, Fremont, CA (US);
Elizabeth Dobisz, Fremont, CA (US);
Mustafa Pinarbasi, Fremont, CA (US);
Integrated Silicon Solution, (Cayman) Inc., Grand Cayman, KY;
Abstract
Embodiments of the present invention include multiple independent terminals for a plurality of devices in a stack configuration within a semiconductor. In one embodiment, a semiconductor comprises: a first device at a first semiconductor level within a multi terminal device stack; wherein the first device is coupled to a first terminal; a second device at a second semiconductor level within the multi terminal device stack, wherein the second device is coupled to a second terminal; a third terminal is coupled to the second device and a fourth terminal is coupled to the first device, wherein the first terminal and second terminal are independently coupled to the first device and second device respectively. The first terminal, the second terminal, the third terminal and the fourth terminal couple components included in the multi terminal stack to components not included in the multi terminal stack.