The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Sep. 08, 2021
Applicant:

Shanghai Biren Technology Co., Ltd, Shanghai, CN;

Inventors:

Shiqun Gu, Shanghai, CN;

Linglan Zhang, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2023.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 23/481 (2013.01); H01L 23/49816 (2013.01); H01L 24/08 (2013.01); H01L 24/80 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80895 (2013.01); H01L 2224/80896 (2013.01);
Abstract

The disclosure provides a chipset and a manufacturing method thereof. The chipset includes multiple logic cores and a memory chip. The logic cores respectively have a first device layer and a first substrate layer, and respectively include multiple first bonding elements and a first input/output circuit. The first bonding elements are provided in the first device layer. The first input/output circuit is provided in the first device layer. The memory chip has a second device layer and a second substrate layer, and includes second bonding elements and second input/output circuits. The second bonding elements are arranged in the second device layer. The second input/output circuits are arranged in the second device layer, and are respectively connected to the first input/output circuits of the logic cores.


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