The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Aug. 16, 2019
Applicants:

Autonetworks Technologies, Ltd., Yokkaichi, JP;

Sumitomo Wiring Systems, Ltd., Yokkaichi, JP;

Sumitomo Electric Industries, Ltd., Osaka, JP;

Inventor:

Akira Haraguchi, Yokkaichi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/07 (2006.01); H01L 23/04 (2006.01); H01L 23/36 (2006.01); H01L 23/492 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01R 9/24 (2006.01); H01R 25/16 (2006.01); H02G 3/16 (2006.01); H05K 1/11 (2006.01); H05K 3/34 (2006.01); H05K 7/14 (2006.01);
U.S. Cl.
CPC ...
H01L 25/072 (2013.01); H01L 23/041 (2013.01); H01L 23/36 (2013.01); H01L 23/492 (2013.01); H01R 9/2466 (2013.01); H01R 25/162 (2013.01); H02G 3/16 (2013.01); H05K 1/115 (2013.01); H05K 7/1432 (2013.01); H05K 7/14322 (2022.08); H01L 23/49838 (2013.01); H01L 23/49861 (2013.01); H01L 23/5386 (2013.01); H01R 2201/26 (2013.01); H05K 3/3447 (2013.01); H05K 2201/09236 (2013.01); H05K 2201/10166 (2013.01); H05K 2201/10272 (2013.01); H05K 2201/10303 (2013.01);
Abstract

A circuit structure includes a plurality of semiconductor elements arranged side by side, and each semiconductor element includes source terminals and at least one gate terminal arranged side by side with the source terminals. The circuit structure includes: a first bus bar connected to the source terminals of the semiconductor elements; connection portions that connect the source terminals and the first bus bar and are arranged side by side along the arrangement direction of the semiconductor elements and whose one ends are connected to the source terminals of the respective semiconductor elements; an insulating portion provided so as to be present between each adjacent pairs of the connection portions; and conductive portions provided in the insulating portion and connected to the gate terminals.


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