The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Feb. 01, 2022
Applicant:

Western Digital Technologies, Inc., San Jose, CA (US);

Inventors:

Haiyue Shen, Shanghai, CN;

Fen Yu, Shanghai, CN;

Hope Chiu, Shanghai, CN;

Donghua Wu, Shanghai, CN;

Hua Tan, Shanghai, CN;

Xinyu Wang, Shanghai, CN;

Shenghua Huang, Shanghai, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/065 (2023.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/0657 (2013.01); H01L 24/48 (2013.01); H01L 2224/48147 (2013.01); H01L 2224/48225 (2013.01); H01L 2225/06562 (2013.01); H01L 2924/1438 (2013.01);
Abstract

A semiconductor memory package includes a substrate, a first stack of memory dies, and a second stack of memory dies. The first stack of memory dies includes a first substack of staggered memory dies offset with respect to each other in a first direction and a second substack of staggered memory dies offset with respect to each other in the first direction and positioned above the first substack. The second stack of memory dies includes a third substack of staggered memory dies offset with respect to each other in a second direction and a fourth substack of staggered memory dies offset with respect to each other in the second direction and positioned above the third substack. The top memory die of the first substack and a memory die positioned below the top memory die of the third substack are at least partially coplanar.


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