Latency-based performance state control

Abstract

Techniques are disclosed relating to controlling performance state of a memory element based on latency information for a processor. In some embodiments, a level of a memory hierarchy is configured to operate at multiple different performance states at different times. Processor circuitry may execute programs that generate requests to access the memory hierarchy. Bandwidth-based control circuitry may generate, based on bandwidth conditions for the processor circuitry, bandwidth performance state signals. Latency-based control circuitry may generate, based on latency information for processor requests to access the memory hierarchy, latency performance state signals. Performance control circuitry may control the performance state of the level of the memory hierarchy based on the bandwidth performance state signals and the latency performance state signals. Disclosed techniques may improve processor performance in certain operating scenarios.