The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Apr. 07, 2023
Applicant:

Cisco Technology, Inc., San Jose, CA (US);

Inventors:

Roman Bruck, Vienna, AT;

Thierry J. Pinguet, Arlington, WA (US);

Attila Mekis, Carlsbad, CA (US);

Assignee:

Cisco Technology, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/132 (2006.01); G02B 6/122 (2006.01); G02B 6/13 (2006.01); G02B 6/136 (2006.01);
U.S. Cl.
CPC ...
G02B 6/122 (2013.01); G02B 6/13 (2013.01); G02B 6/132 (2013.01); G02B 6/136 (2013.01);
Abstract

End-face coupling structures within an electrical backend are provided via photonic integrated circuit (PIC), comprising: a first plurality of spacer layers; a second plurality of etch-stop layers, wherein each etch-stop layer of the second plurality of etch-stop layers is located between two spacer layers of the first plurality of spacer layers; and an optical coupler comprising a plurality of waveguides arranged as a waveguide array configured to receive an optical signal in a direction of travel, wherein each waveguide of the plurality of waveguides is located at a layer interface defined between an etch-stop layer and a spacer layer. Portions of the PIC can be formed by depositing layers of spacer and etch-stop materials in which cavities are formed to define the waveguides when the waveguide material is deposited or interconnects when a metal is deposited therein.


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