The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 02, 2024

Filed:

Oct. 18, 2022
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Prasanth Viswanathan Pillai, Bangalore, IN;

Rajeev Suvarna, Bangalore, IN;

Saya Goud Langadi, Sugarland, TX (US);

Shailesh Ganapat Ghotgalkar, Bangalore, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/06 (2006.01); G01R 31/3177 (2006.01); G01R 31/3185 (2006.01); G01R 31/3187 (2006.01); G06F 11/10 (2006.01); G06F 12/0804 (2016.01); G06F 13/16 (2006.01); H03K 3/037 (2006.01); H03K 5/24 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/3187 (2013.01); H03K 3/037 (2013.01); H03K 5/24 (2013.01); H03K 19/003 (2013.01); G01R 31/318566 (2013.01);
Abstract

Lockstep comparators and related methods are described. An example apparatus includes self-test logic circuitry having first outputs, and comparator logic including selection logic having first inputs and second outputs, ones of the first inputs coupled to the first outputs, first detection logic having second inputs and third outputs, the second inputs coupled to the second outputs, second detection logic having third inputs and fourth outputs, the third inputs coupled to the third outputs, latch logic having fifth inputs and fifth outputs, the third output and the fourth output coupled to the fifth inputs, and error detection logic having sixth inputs coupled to the fifth inputs.


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