The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Mar. 06, 2019
Applicant:

Samsung Display Co., Ltd., Yongin-Si, KR;

Inventors:

Seunghun Lee, Seoul, KR;

Myounghwa Kim, Seoul, KR;

Jaybum Kim, Seoul, KR;

Kyoung-seok Son, Seoul, KR;

Seungjun Lee, Suwon-si, KR;

Jun-hyung Lim, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/131 (2023.01); H10K 71/00 (2023.01); H10K 50/844 (2023.01); H10K 59/12 (2023.01); H10K 77/10 (2023.01); H10K 102/00 (2023.01);
U.S. Cl.
CPC ...
H10K 59/1315 (2023.02); H10K 71/00 (2023.02); H10K 50/844 (2023.02); H10K 59/1201 (2023.02); H10K 77/111 (2023.02); H10K 2102/311 (2023.02);
Abstract

An organic light emitting display device includes a substrate including a light emitting region, a first active layer having a source region and a drain region disposed in the light emitting region on the substrate, a gate insulation layer disposed on the first active layer, a first gate electrode disposed on the gate insulation layer, a first insulating interlayer disposed on the first gate electrode, a second insulating interlayer disposed on the first insulating interlayer, a first source electrode disposed on the second insulating interlayer, the first source electrode being connected to the source region of the first active layer through a contact hole formed in the gate insulation layer, the first insulating interlayer, and the second insulating interlayer, a protective insulating layer disposed on the first source electrode, a first drain electrode disposed on the protective insulating layer, the first drain electrode being connected to the drain region of the first active layer through a contact hole formed in the gate insulation layer, the first insulating interlayer, and the protective insulating layer, the first drain electrode constituting a driving transistor together with the first active layer, the first gate electrode, and the first source electrode, a switching transistor disposed in the second region between the substrate and the protective insulating layer, a lower electrode disposed on the switching transistor and the driving transistor, a light emitting layer disposed on the lower electrode, and an upper electrode disposed on the light emitting layer.


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