The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Mar. 02, 2021
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Tae Jong Eom, Cheonan-si, KR;

Chun Gi You, Asan-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Yongin-si, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H10K 59/131 (2023.01); H01L 23/00 (2006.01); H10K 59/121 (2023.01);
U.S. Cl.
CPC ...
H10K 59/131 (2023.02); H01L 24/05 (2013.01); H01L 24/16 (2013.01); H01L 24/32 (2013.01); H01L 24/73 (2013.01); H01L 2224/02331 (2013.01); H01L 2224/02373 (2013.01); H01L 2224/02375 (2013.01); H01L 2224/02379 (2013.01); H01L 2224/02381 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/05569 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/32148 (2013.01); H01L 2224/73203 (2013.01); H01L 2924/01022 (2013.01); H01L 2924/01042 (2013.01); H10K 59/1213 (2023.02);
Abstract

A display device includes: a substrate; sub-pixels on the substrate; data lines connected to the sub-pixels; a display driving circuit supplying data voltages to the data lines; and fan-out lines on the substrate and connecting the data lines and the display driving circuit. Each of the sub-pixels includes a first transistor including a first active layer on the substrate and including a silicon semiconductor and a first gate electrode on the first active layer, and a second transistor including a second active layer on the substrate and including an oxide semiconductor and a second gate electrode on the second active layer. The fan-out lines include first fan-out lines and second fan-out lines alternately arranged each other in one direction. The first fan-out lines are arranged on the same layer as the first gate electrode, and the second fan-out lines are arranged on the same layer as the second gate electrode.


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