The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Oct. 07, 2021
Applicants:

Samuel Ahn, Marina Del Rey, CA (US);

Dmitry Ryuma, Sherman Oaks, CA (US);

Richard Zhuang, San Diego, CA (US);

Inventors:

Samuel Ahn, Marina Del Rey, CA (US);

Dmitry Ryuma, Sherman Oaks, CA (US);

Richard Zhuang, San Diego, CA (US);

Assignee:

Snap Inc., Santa Monica, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04W 56/00 (2009.01); G02B 27/01 (2006.01); G06F 1/10 (2006.01); G06F 1/12 (2006.01); G06F 13/24 (2006.01); G06F 13/40 (2006.01); H04J 3/06 (2006.01);
U.S. Cl.
CPC ...
H04J 3/065 (2013.01); G02B 27/017 (2013.01); G06F 1/10 (2013.01); G06F 1/12 (2013.01); G06F 13/24 (2013.01); G06F 13/4068 (2013.01); G02B 2027/0178 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/0038 (2013.01);
Abstract

An electronic eyewear device includes first and second systems-on-chip (SoCs) having independent time bases. The first and second SoCs are connected by a shared general purpose input/output (GPIO) connection and an inter-SoC interface. The first and second SoCs are synchronized to each other by the first SoC asserting the shared GPIO connection to the second SoC where assertion of the message to the shared GPIO connection triggers an interrupt request (IRQ) at the second SoC. The first SoC records a first timestamp for assertion of the message to the GPIO connection, and the second SoC records a second timestamp of receipt of the IRQ. The first SoC sends a message including the first timestamp to the second SoC over the inter-SoC interface. The second SoC calculates a clock offset between the first and second SoCs as a difference between the first and second timestamps.


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