The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Mar. 01, 2022
Applicant:

Sandeep Kumar Gupta, Sunny Isles Beach, FL (US);

Inventor:

Sandeep Kumar Gupta, Sunny Isles Beach, FL (US);

Assignee:

Zeta Gig Inc., Sunny Isles Beach, FL (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/08 (2006.01); H03K 19/0185 (2006.01); H03K 19/17784 (2020.01); H03K 19/20 (2006.01);
U.S. Cl.
CPC ...
H03K 19/0813 (2013.01); H03K 19/018585 (2013.01); H03K 19/17784 (2013.01); H03K 19/20 (2013.01);
Abstract

Apparatuses, and methods, for digital cells power reduction are disclosed. For an embodiment, a first plurality of digital logic cells are directly connected to a Vdd terminal and a Vss terminal that have a potential difference of VDD, a second plurality of digital logic cells being directly connected to a Vdd_R terminal and a Vss_R terminal, wherein a potential difference between the Vdd_R terminal and the Vss terminal is (VDD−X1), and a potential difference between the Vss_R terminal and the Vss terminal is X2, wherein at least one digital logic cell has at least one of (a) an input connected to an output of at least one digital logic cell of the second plurality, or (b) an output connected to an input of at least one digital logic cell of the second plurality. Vdd, Vdd_R and Vss_R terminal voltages can be generated by an array of devices.


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