The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2024
Filed:
Nov. 10, 2021
Electronics and Telecommunications Research Institute, Daejeon, KR;
Korea Advanced Institute of Science and Technology, Daejeon, KR;
Chi-Sun Hwang, Daejeon, KR;
SangHee Park, Daejeon, KR;
KwangHeum Lee, Daejeon, KR;
Jae-Eun Pi, Sejong-si, KR;
SeungHee Lee, Daejeon, KR;
Jong-Heon Yang, Daejeon, KR;
Ji Hun Choi, Daejeon, KR;
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE, Daejeon, KR;
KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY, Daejeon, KR;
Abstract
A vertical channel thin film transistor includes substrate, lower source/drain electrode, spacer layer, upper source/drain electrode covering portion of upper surface of the spacer layer, interlayer insulating pattern covering portion of upper surface of the upper source/drain electrode and upper surface of the spacer layer exposed by the upper source/drain electrode, contact hole disposed on the lower source/drain electrode and passing through the interlayer insulating pattern, the upper source/drain electrode, and the spacer layer, active pattern covering inner wall and bottom surface of the contact hole and extending over upper surface of the upper source/drain electrode and upper surface of the interlayer insulating pattern, gate insulating pattern filling portion of the contact hole and extending along upper surface of the active pattern, and gate electrode filling portion of the contact hole and extending along upper surface of the gate insulating pattern.