The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2024
Filed:
Sep. 25, 2020
Fuzhou Boe Optoelectronics Technology Co., Ltd., Fujian, CN;
Boe Technology Group Co., Ltd., Beijing, CN;
Bin Lin, Beijing, CN;
Yong Zeng, Beijing, CN;
Yazhou Huo, Beijing, CN;
Liangliang Li, Beijing, CN;
Zhouyu Chen, Beijing, CN;
FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., Fujian, CN;
BOE TECHNOLOGY GROUP CO., LTD., Beijing, CN;
Abstract
The present disclosure provides an array substrate and a preparation method thereof, belonging to the field of display technology. The preparation method of the array substrate includes: providing a base substrate; forming a common electrode bonding line on one side of the base substrate; forming an oxide semiconductor material layer, and the oxide semiconductor material layer and the common electrode bonding line are located on the base substrate on the same side, and the oxide semiconductor material layer is electrically connected to at least part of the common electrode bonding line; the oxide semiconductor material layer is patterned to form an oxide semiconductor layer with multiple active layers, and the oxide semiconductor layer is The orthographic projection on the base substrate and the common electrode bonding line overlap at most parts of the orthographic projection on the base substrate, and any active layer and the common electrode bonding line are insulated from each other. The preparation method of the array substrate can avoid electrostatic breakdown of the array substrate during the preparation process.