The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Sep. 14, 2022
Applicant:

Stmicroelectronics S.r.l., Agrate Brianza, IT;

Inventors:

Paolo Colpani, Agrate Brianza, IT;

Samuele Sciarrillo, Usmate Velate, IT;

Ivan Venegoni, Bareggio, IT;

Francesco Maria Pipia, Milan, IT;

Simone Bossi, Arese, IT;

Carmela Cupeta, Milan, IT;

Assignee:

STMICROELECTRONICS S.r.l., Agrate Brianza, IT;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01);
U.S. Cl.
CPC ...
H01L 24/03 (2013.01); H01L 21/02164 (2013.01); H01L 21/0217 (2013.01); H01L 21/76802 (2013.01); H01L 21/76877 (2013.01); H01L 23/528 (2013.01); H01L 24/05 (2013.01); H01L 2224/0231 (2013.01); H01L 2224/0233 (2013.01); H01L 2224/0239 (2013.01); H01L 2224/024 (2013.01); H01L 2224/03464 (2013.01); H01L 2224/03614 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05024 (2013.01); H01L 2224/05083 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05155 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05184 (2013.01); H01L 2224/05664 (2013.01); H01L 2924/01028 (2013.01); H01L 2924/01029 (2013.01); H01L 2924/01046 (2013.01); H01L 2924/0132 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/20102 (2013.01); H01L 2924/20103 (2013.01); H01L 2924/20104 (2013.01); H01L 2924/20105 (2013.01); H01L 2924/20106 (2013.01); H01L 2924/20107 (2013.01);
Abstract

A method of manufacturing a redistribution layer includes: forming an insulating layer on a wafer, delimited by a top surface and a bottom surface in contact with the wafer; forming a conductive body above the top surface of the insulating layer; forming a first coating region extending around and above the conductive body, in contact with the conductive body, and in contact with the top surface of the insulating layer in correspondence of a bottom surface of the first coating region; applying a thermal treatment to the wafer in order to modify a residual stress of the first coating region, forming a gap between the bottom surface of the first coating region and the top surface of the insulating layer; forming, after applying the thermal treatment, a second coating region extending around and above the first coating region, filling said gap and completely sealing the first coating region.


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