The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 25, 2024
Filed:
Jul. 15, 2021
Xilinx, Inc., San Jose, CA (US);
Karthic P, Chennai, IN;
Paul Kundarewich, Toronto, CA;
Satish Sivaswamy, Fremont, CA (US);
Meghraj Kalase, Hyderabad, IN;
Vishal Tripathi, Hyderabad, IN;
Srinivasan Dasasathyan, Secunderabad, IN;
Mehrdad Eslami Dehkordi, Los Gatos, CA (US);
Xiaojian Yang, Santa Clara, CA (US);
Amish Pandya, San Ramon, CA (US);
XILINX, INC., San Jose, CA (US);
Abstract
Methods and systems for selecting between single-process and multi-process implementation flows involve identifying features of a circuit design by a design tool. A classification model is applied to the features. The classification model indicates whether an implementation flow on the circuit design is likely to have a runtime within a first range of runtimes or a runtime within a second range of runtimes. The implementation flow is executed by the design tool in a single process in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the first range of runtimes. The implementation flow is executed by the design tool in a plurality of processes in response to the classification model indicating the implementation flow on the circuit design is likely to have a runtime within the second range of runtimes.