The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Oct. 30, 2018
Applicant:

Nvidia Corporation, Santa Clara, CA (US);

Inventors:

Thomas E. Dewey, Menlo Park, CA (US);

Narayan Kulshrestha, Fremont, CA (US);

Ramachandiran V, Bangalore, IN;

Sachin Idgunji, San Jose, CA (US);

Lordson Yue, Los Altos, CA (US);

Assignee:

NVIDIA CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2019.01); G06F 1/3234 (2019.01); G06F 1/3287 (2019.01); G06F 1/3296 (2019.01); G06F 13/42 (2006.01); G06F 15/78 (2006.01); G06T 1/20 (2006.01); G06T 15/00 (2011.01);
U.S. Cl.
CPC ...
G06F 1/3287 (2013.01); G06F 1/3243 (2013.01); G06F 1/3278 (2013.01); G06F 1/3296 (2013.01); G06F 13/4221 (2013.01); G06F 15/7807 (2013.01); G06T 1/20 (2013.01); G06T 15/005 (2013.01); G06F 2213/0026 (2013.01);
Abstract

An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.


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