The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 25, 2024

Filed:

Dec. 15, 2021
Applicant:

Movellus Circuits Incorporated, Ann Arbor, MI (US);

Inventors:

Jeffrey Alan Fredenburg, Chicago, IL (US);

Mohammad Faisal, San Francisco, CA (US);

David Moore, Ann Arbor, MI (US);

Yu Huang, Ann Arbor, MI (US);

Assignee:

Movellus Circuits Inc., Ann Arbor, MI (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 1/10 (2006.01); H01L 25/065 (2023.01); H03L 7/00 (2006.01); H03L 7/081 (2006.01); H03L 7/083 (2006.01); H03L 7/099 (2006.01);
U.S. Cl.
CPC ...
G06F 1/10 (2013.01); H01L 25/0657 (2013.01); H03L 7/00 (2013.01); H03L 7/0816 (2013.01); H03L 7/0818 (2013.01); H03L 7/083 (2013.01); H03L 7/0991 (2013.01); H01L 2924/18161 (2013.01);
Abstract

A semiconductor package includes source clock circuitry to generate a source clock signal. Reference clock circuitry generates a reference clock signal. A first timing circuit includes a first source clock input to receive the source clock signal. First fan-out circuitry distributes the received source clock signal as a first distributed clock signal to a first set of clocked devices. A first delay circuit delays the received source clock signal by a first delay value based on a first phase difference between the first distributed clock signal and the reference clock signal.


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