The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Jan. 04, 2021
Applicant:

Samsung Display Co., Ltd., Yongin-si, KR;

Inventors:

Junehwan Kim, Yongin-si, KR;

Taeyoung Kim, Yongin-si, KR;

Jongwoo Park, Yongin-si, KR;

Kiju Im, Yongin-si, KR;

Hyuncheol Hwang, Yongin-si, KR;

Assignee:

SAMSUNG DISPLAY CO., LTD., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10K 59/12 (2023.01); G09G 3/3233 (2016.01); H01L 29/10 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H10K 10/46 (2023.01); H10K 59/121 (2023.01); H10K 59/35 (2023.01); H10K 77/10 (2023.01); H10K 102/00 (2023.01);
U.S. Cl.
CPC ...
H10K 59/12 (2023.02); G09G 3/3233 (2013.01); G09G 2320/0233 (2013.01); H01L 29/1054 (2013.01); H01L 29/66757 (2013.01); H01L 29/7842 (2013.01); H01L 29/78666 (2013.01); H01L 29/78675 (2013.01); H01L 2924/13069 (2013.01); H10K 10/464 (2023.02); H10K 59/1213 (2023.02); H10K 59/35 (2023.02); H10K 77/111 (2023.02); H10K 2102/311 (2023.02);
Abstract

A display device having a thin-film transistor with increased mobility of electrons or holes includes a first semiconductor layer arranged on a substrate and including a first channel region, a first source region, and a first drain region; a first stressor arranged between the substrate and the first semiconductor layer and which overlaps the first source region in a plan view; a second stressor arranged between the substrate and the first semiconductor layer and which overlaps the first drain region in the plan view, where the second stressor is spaced apart from the first stressor; a gate insulating layer arranged on the first semiconductor layer; and a first gate electrode arranged on the gate insulating layer and which overlaps the first semiconductor layer in the plan view.


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