The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Jan. 17, 2023
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Kyoung-Hee Kim, Hwaseong-si, KR;

Woo Choel Noh, Hwaseong-si, KR;

Ik Soo Kim, Yongin-si, KR;

Jun Kwan Kim, Seoul, KR;

Jinsub Kim, Seoul, KR;

Yongjin Shin, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H10B 41/46 (2023.01); H10B 41/10 (2023.01); H10B 41/20 (2023.01); H10B 43/10 (2023.01); H10B 43/20 (2023.01); H10B 43/40 (2023.01);
U.S. Cl.
CPC ...
H10B 41/46 (2023.02); H10B 41/10 (2023.02); H10B 41/20 (2023.02); H10B 43/10 (2023.02); H10B 43/20 (2023.02); H10B 43/40 (2023.02);
Abstract

A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.


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