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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 12015056 B1

PDFFull Text
Date of Patent:
Jun. 18, 2024

Filed:

Apr. 25, 2023

Field effect transistor with controllable resistance

Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Yulong Li, Westchester, NY (US);

Paul M. Solomon, Westchester, NY (US);

Siyuranga Koswatta, Carmel, NY (US);

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US);

Attorneys:

CANTOR COLBURN LLP

Daniel Yeates

Primary Examiner:

Walter H Swanson

Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 21/28 (2006.01); H01L 29/06 (2006.01); H01L 29/165 (2006.01); H01L 29/205 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 29/68 (2006.01); H01L 29/78 (2006.01); H01L 29/788 (2006.01); H01L 29/80 (2006.01); H10B 12/00 (2023.01); H10B 41/30 (2023.01); H10B 51/30 (2023.01); H10B 63/00 (2023.01);
U.S. Cl.
CPC ...
H01L 29/1045 (2013.01); H01L 29/0646 (2013.01); H01L 29/1054 (2013.01); H01L 29/165 (2013.01); H01L 29/205 (2013.01); H01L 29/40111 (2019.08); H01L 29/40114 (2019.08); H01L 29/42324 (2013.01); H01L 29/4983 (2013.01); H01L 29/516 (2013.01); H01L 29/66431 (2013.01); H01L 29/66659 (2013.01); H01L 29/66977 (2013.01); H01L 29/685 (2013.01); H01L 29/785 (2013.01); H01L 29/7881 (2013.01); H01L 29/802 (2013.01); H10B 12/30 (2023.02); H10B 41/30 (2023.02); H10B 51/30 (2023.02); H10B 63/00 (2023.02); H01L 29/66825 (2013.01); H01L 29/6684 (2013.01); H01L 29/78391 (2014.09); H01L 29/788 (2013.01);
Abstract

A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

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