The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Dec. 30, 2020
Applicants:

Beijing Boe Optoelectronics Technology Co., Ltd., Beijing, CN;

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Wei Chen, Beijing, CN;

Weixiong Chen, Beijing, CN;

Xin Li, Beijing, CN;

Yong Song, Beijing, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); G02F 1/1362 (2006.01); G02F 1/1368 (2006.01); G09G 3/36 (2006.01); G02F 1/1333 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
H01L 27/124 (2013.01); G02F 1/136286 (2013.01); G02F 1/1368 (2013.01); G09G 3/3622 (2013.01); H01L 27/1259 (2013.01); G02F 1/133331 (2021.01); G09G 2300/0408 (2013.01); G09G 2310/0281 (2013.01); G09G 2310/0283 (2013.01); G09G 2310/0286 (2013.01); G09G 2320/0233 (2013.01); G11C 19/28 (2013.01);
Abstract

An array substrate includes a base, a first conductive layer disposed at a side of the base, an insulating layer disposed at a side of the first conductive layer away from the base, and a second conductive layer disposed at a side of the insulating layer away from the first conductive layer. The insulating layer is provided with a first via hole exposing the first electrode of the first transistor and a second via hole exposing the first electrode of the second transistor. The second conductive layer includes a first conductive connection portion, and the first conductive connection portion connects the first electrode of the first transistor and the first electrode of the second transistor through the first via hole and the second via hole.


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