The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Sep. 27, 2021
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Yuki Fujita, Kanagawa, JP;

Kei Kitamura, Kanagawa, JP;

Kyosuke Matsumoto, Kanagawa, JP;

Masahiro Kano, Kanagawa, JP;

Minoru Yamashita, Kanagawa, JP;

Ryuji Yamashita, Tokyo, JP;

Shuzo Otsuka, Kanagawa, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/06 (2006.01); G11C 7/10 (2006.01); G11C 7/12 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01);
U.S. Cl.
CPC ...
G11C 7/06 (2013.01); G11C 7/1048 (2013.01); G11C 7/12 (2013.01); G11C 16/102 (2013.01); G11C 16/26 (2013.01);
Abstract

A method for programming a non-volatile memory structure, wherein the method comprises initiating a two-dimensional fractional number of bits-per-cell programming scheme with respect to at least a first memory cell and a second memory cell of a plurality of memory cells of the memory structure, wherein the memory structure comprises: (1) a first memory array that comprises a first population of the plurality of memory cells and associated peripheral circuitry disposed below the first population of the plurality of memory cells, (2) a second memory array that is positioned above the first memory array and comprises a second population of the plurality of memory cells and the associated peripheral circuitry that is disposed above the second population of the plurality of memory cells, and (3) a data bus tap electrically coupling the first memory array and the second memory array.


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