The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 18, 2024

Filed:

Oct. 31, 2022
Applicant:

Lg Display Co., Ltd., Seoul, KR;

Inventors:

Daeyoung Seo, Paju-si, KR;

YoungIn Jang, Paju-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/3266 (2016.01); G09G 3/20 (2006.01); G11C 19/28 (2006.01);
U.S. Cl.
CPC ...
G09G 3/3266 (2013.01); G09G 3/2092 (2013.01); G11C 19/28 (2013.01); G09G 2300/0852 (2013.01); G09G 2310/0267 (2013.01); G09G 2310/0275 (2013.01); G09G 2310/0291 (2013.01); G09G 2310/08 (2013.01);
Abstract

Disclosed is a gate driving circuit comprising a plurality of stage circuits dependently connected to each other and configured to output 'j' output signals ('j' is an integer of 2 or more), wherein each of the plurality of stage circuits includes a logic controller for controlling a voltage of each of first and second nodes, and an output circuit unit for outputting each of ‘j’ clock signals as the ‘j’ output signal in response to the voltage of the first node, wherein the output circuit unit includes ‘j’ output buffers for outputting each of the ‘j’ clock signals as the ‘j’ output signal through an output node in response to the voltage of the first node, and a capacitor prepared between the first node and the output node of some of the ‘j’ output buffers.


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