The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2024
Filed:
Oct. 31, 2022
Applicant:
Newport Fab, Llc, Newport Beach, CA (US);
Inventors:
Edward Preisler, San Clemente, CA (US);
Zhirong Tang, Lake Oswego, OR (US);
Assignee:
Newport Fab, LLC, Newport Beach, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/02 (2006.01); H01L 25/16 (2023.01); H01L 31/0224 (2006.01); H01L 31/0232 (2014.01); H01L 31/0304 (2006.01); H01L 31/109 (2006.01); H01L 31/18 (2006.01);
U.S. Cl.
CPC ...
H01L 31/02005 (2013.01); H01L 25/167 (2013.01); H01L 31/022408 (2013.01); H01L 31/02325 (2013.01); H01L 31/0304 (2013.01); H01L 31/109 (2013.01); H01L 31/184 (2013.01);
Abstract
A semiconductor structure includes a group IV substrate and a patterned group III-V device over the group IV substrate. A blanket dielectric layer is situated over the patterned group III-V device. Contact holes in the blanket dielectric layer are situated over the patterned group III-V device. A liner stack having at least one metal liner is situated in each contact hole. Filler metals are situated over each liner stack and fill the contact holes. The patterned group III-V device can be optically and/or electrically connected to group IV devices in the group IV substrate.