The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2024
Filed:
Jan. 05, 2022
Applicant:
Db Hitek Co., Ltd., Bucheon-si, KR;
Inventors:
Yong Sin Han, Jeonju-si, KR;
Myeong Bum Pyun, Incheon, KR;
Assignee:
DB HiTek, Co., Ltd., Bucheon-si, KR;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/739 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 29/0623 (2013.01); H01L 29/0634 (2013.01); H01L 29/402 (2013.01); H01L 29/42376 (2013.01); H01L 29/66333 (2013.01); H01L 29/66712 (2013.01); H01L 29/7395 (2013.01); H01L 29/7811 (2013.01); H01L 29/42368 (2013.01);
Abstract
Disclosed are a superjunction semiconductor device and a method of manufacturing the same. More particularly, the present disclosure relates to a superjunction semiconductor device and a method of manufacturing the same, in which the device includes a field oxide layer having an uppermost end or surface that is higher than that of a gate oxide layer, between a gate electrode and a second pillar region in a cell region. This enables a reduction in gate-drain parasitic capacitance, thereby increasing switching speed and reducing switching loss.