The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 11, 2024
Filed:
Jul. 28, 2016
Applicant:
Mitsubishi Electric Corporation, Tokyo, JP;
Inventors:
Yosuke Nakata, Tokyo, JP;
Taishi Sasaki, Tokyo, JP;
Assignee:
Mitsubishi Electric Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 21/52 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 24/32 (2013.01); H01L 21/52 (2013.01); H01L 23/48 (2013.01); H01L 24/29 (2013.01); H01L 24/30 (2013.01); H01L 24/33 (2013.01); H01L 24/83 (2013.01); H01L 2224/26155 (2013.01); H01L 2224/29155 (2013.01); H01L 2224/30181 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/33181 (2013.01); H01L 2224/83007 (2013.01); H01L 2224/83065 (2013.01); H01L 2224/83815 (2013.01); H01L 2924/014 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/351 (2013.01);
Abstract
A semiconductor chip () is bonded to an upper surface of an electrode substrate () via a first solder (). A lead frame () is bonded to an upper surface of the semiconductor chip () via a second solder (). An intermediate plate () is provided in the first solder () between the electrode substrate () and the semiconductor chip (). A yield strength of the intermediate plate () is higher than yield strengths of the electrode substrate () and the first solder () within the whole operating temperature range of the semiconductor device.